A phase-locked loop (PLL) is an electronic circuit with a voltage or voltage-driven oscillator that constantly adjusts to match the frequency of an input signal. PLLs are often incorporated into integrated circuit (IC) devices, and are often used in systems utilizing two clock signals to help align the two clock signals.
Referring to FIG. 7A, a conventional PLL circuit 50 includes a phase frequency detector (PFD) 54 that outputs pump control voltages VUP and VDOWN having values based on the phase difference between an input signal frequency FINF and a feedback signal frequency FFB, a charge pump 58 that generates an output current ICP-OUT in accordance with the pump control voltages that produces a charge stored on a loop filter 64, thereby converting the phase difference between FINF and FFB to a controlled voltage (VCONT). A voltage controlled oscillator (VCO) 52 generates a PLL output signal OUTF having a frequency FVCO determined by the voltage level of controlled voltage VCONT. A digital divider 60 divides output signal frequency FVCO by a predetermined integer or fractional value N to generate a feedback signal FB. Level shifters 56 may be utilized to match the voltage levels of an input signal INF and the feedback signal FB generated by loop divider 60, whereby input signal frequency FINF and feedback signal frequency FFB supplied to PFD 54 have properly matched voltage levels.
FIG. 7B is a timing diagram indicating the relationship between pump control voltages VUP and VDOWN generated by PFD 54 and the operation of charge pump 58. Referring to FIG. 7A, charge pump 58 generally utilizes a pull-up (e.g., PMOS) transistor 59A controlled by pump control signal VUP and a pull-down (e.g., NMOS) transistor 59B controlled by pump control signal VDOWN to either increase, maintain or decrease controlled voltage VCONT. As indicated between times T1 and T3 in FIG. 7B, when the phase of the feedback signal frequency FFB lags the phase of the input signal frequency FINF (FINF>FFB), PFD 54 asserts pump control voltage VUP at a low voltage level and output control voltage VDOWN at a high voltage level such that the pull-down NMOS transistor 59B is turned off and the pull-up PMOS transistor 59A is turned on, thereby coupling the output terminal of charge pump 58 to system voltage VDD such that output current ICP-OUT has a positive (UP) current value determined by positive current component IUP. The positive output current ICP-OUT then increases the controlled voltage VCONT at the output of the charge pump 58 by increasing the charge stored on loop filter (capacitive circuit) 64, which in turn causes VCO 52 to increase the output signal frequency FVCO of output signal OUTF. Conversely, as indicated between times T0 and T1 and between times T3 and T4 in FIG. 7B, when the feedback signal frequency FFB leads the phase of the input signal frequency FINF, PFD 54 generates pump control voltages VUP and VDOWN such that pull-down NMOS transistor 59B is turned on and pull-up PMOS transistor 59A is turned off, whereby the output terminal of charge pump 58 is coupled to ground and pump output current ICP-OUT has a negative (DOWN) current value determined by negative current value IDOWN. The negative output current ICP-OUT then decreases controlled voltage VCONT by discharging a portion of the charge stored on the capacitive circuit 64, which in turn causes VCO 52 to decrease the output signal frequency FVCO of output signal OUTF. In this manner output frequency FVCO is continuously adjusted until the phases of input signal frequency FINF and the feedback clock signal frequency FFB align (match), whereby, as indicated between times T4 and T5 in FIG. 7B, pump control voltages VUP and VDOWN are generated such that both pull-up PMOS transistor 59A and pull-down NMOS transistor 59B are turned off, whereby the controlled voltage VCONT is maintained at its current voltage level, in turn causing the VCO 52 to generate output signal OUTF at signal frequency FVCO corresponding to the matched phases.
A problem with the conventional approach is that, due to various factors, the magnitude of the positive current corresponding to the UP current component IUP generated during leading periods becomes mismatched with the magnitude of the negative current corresponding to the DOWN current component IDOWN generated during the lagging periods. That is, the average charges accumulated on the loop filter 64 due to the UP and DOWN currents (average charge=current*time) become mismatched, for example, due to the finite output resistance of the pull-up and pull-down current sources utilized to generate the UP and DOWN currents, variation of controlled voltage VCONT over time, controlled voltage and temperature variations over time, time delay differences between the UP and DOWN currents, and charge injection and charge coupling phenomena that take place inside the charge pump 58. Referring to FIG. 7B, this mismatch is illustrated by way of depicting DOWN current component IDOWN as having a larger magnitude of 3.5 μA (i.e., the absolute value of −3.5 μA) than the magnitude of UP current IUP (i.e., 3 μA).
The mismatch between the UP current component IUP and the DOWN current component IDOWN result in spurious electrical effects (spurs) which cause phase errors between the input signal frequency FINF and the feedback signal frequency FFB. This phase error is called static phase error. In a fractional PLL in which the loop divider 60 divides output frequency FVCO by fractional number N to generate the feedback signal frequency FFB, this mismatch is highly undesirable as due to the non-linearity in the charge pump 58, spurs are produced at lower frequencies in-band, which worsens the integrated jitter of PLL 50.
Some prior attempts to address mismatches in the charge pump 58 include increases the output impedance of the source and sink current sources utilized to generate the UP and DOWN current components using impedance boosting architectures such as cascoding. This solution may be impractical when conventional PLL 50 operates at lower voltages and/or wide band frequencies. Another conventional mitigation approach involves reducing offsets in the UP and DOWN current paths between the phase frequency detector 54 and the charge pump 58 with careful layout design. Charge injection and charge coupling are difficult to mitigate, although TX gates (transmission gates, electronic components that will selectively block or pass a signal level from the input to the output) are sometimes used for this purpose.
In U.S. Pat. No. 7,009,432, entitled “Self-calibrating phase locked loop charge pump system and method”, a circuit is described to reduce current mismatch between the UP and DOWN currents. However, the circuit does not cancel the timing mismatch between the UP and DOWN paths in the combined phase frequency detector 54 and charge pump 58 circuit block.
What is needed is a PLL circuit and an associated operating method that addresses the problems associated with conventional PLLs that are set forth above.